This invention relates to a construction of a semiconductor device having a field-effect transistor (hereinafter referred to it as FET), and a manufacturing method thereof.
A conventional semiconductor device having a FET (especially, MOSFET having a gate insulating Film) is shown in FIG. 12. In detail, a gate electrode 12 is provided on a silicon substrate 10 of a conductive type via a gate insulating film. A gate region 17 to which an impurity for adjusting threshold, namely an impurity of the same conductive type as that of the silicon substrate 10 is doped, is formed under the gate electrode 12 in the silicon substrate 10. A drain region 16 and a source region 15 are doped with an impurity of an inverse conductive type to that of the silicon substrate 10 and are formed on sides of the gate electrode 12 in the silicon substrate 10. Under such a construction, a current between source and drain is adjusted according to a bias voltage to the gate electrode 12. Each isolation 11 such as LOCOS is provided so as to electrically insulate a region Rfet at which the MOSFET is to be formed from other regions. Further, a channel stop region 13a to which an impurity is doped is provided under the isolation 11 to ensure the characteristic of isolation.
FIGS. 13(a)-(e) show a manufacturing process of an n-channel MOSFET of such FETs.
First, as shown in FIG. 13(a), a silicon nitride layer 31 open to a region 31a at which an isolation is to be formed is formed on a p-type silicon substrate 10 (or p-well), and a p-type impurity (boron, or the like) for forming the channel stop region is implanted.
Next, as shown in FIG. 13(b), the isolation 11 made of LOCOS is formed at the open part 31a of the silicon nitride layer 31 by thermal oxidation. At this time, the p-type impurity which is previously implanted is diffused to form the channel stop region 13a.
Then, as shown in FIG. 13(c), after removing the silicon nitride layer 31, a silicon oxide layer 33 is formed on the silicon substrate 10 and phosphorous, as an impurity for adjusting threshold, is implanted thereover. Wherein, the region at which other elements such as the p-channel MOSFET are to be formed is covered with a photoresist mask.
Then, as shown in FIG. 13(d), after removing the silicon oxide layer 33, a clean gate insulating film 18 (silicon oxide layer or double layer of silicon oxide layer and silicon nitride layer) is formed and a gate electrode 12 made of polysilicon is formed thereon.
Then, as shown in FIG. 13(e), an impurity, whose density is high, of the inverse conductive type to the silicon substrate 10, e.g. arsenic, is implanted to form a source region 15 and a drain region 16, using, as masks, the gate electrode 12 and a photoresist mask 32 open to a region surrounded by the isolation 11.
When the isolation 11 is wide and thick enough in such a MOSFET which is not so highly integrated, the impurity density of the channel stop region 13a is not necessarily so high, and about 5.times.10.sup.16 cm.sup.-3 is enough impurity density to obtain an excellent characteristic of element isolation. However, isolation becomes narrower accompanied by high-density elements, so that growth of the thick oxide layer in the narrower isolation is difficult and unfavorable in view of reduction of step difference. The oxide layer of the isolation should be thin. However, such a thin oxide layer of the isolation makes the isolation characteristic lowered unless the impurity density of the channel stop region 13a is high. For example, with 0.6 .mu. isolation width and oxide layer of 300 nm thickness, the impurity density of the channel stop region 13a must be higher than about 1.times.10.sup.17 cm.sup.-3 to ensure the characteristic of isolation. When the impurity density is about 5.times.10.sup.16 cm.sup.-3 a durability to high voltage at a boundary between the channel stop region 13a (p-type) and the drain region 16 (n-type), i.e. a P-N junction part is not lowered. However, when the impurity density of the channel stop region 13a is about 1.times.10.sup.17 cm.sup.-3 the durability to high voltage at the P-N junction part is lowered because a depletion region is prevented from dispersion.
In order to solve this problem, Japanese Patent Application Laying Open Gazette No.3-283574 discloses a construction shown in FIGS. 14(a)-(d). FIG. 14(a)) is a plan view of the semiconductor device, FIGS. 14(b), (c) and (d) are respectively sections taken along lines XIVb--XIVb, XIVc--XIVc and XIVd--XIVd. Each figure shows that the channel stop region 13a is offset to a side of the isolation 11 by a set distance from the isolation 11, instead of the channel stop region 13a having comparatively high impurity density being provided on the whole region under the isolation 11. In other words, an offset region 20 having low impurity density over a set width is formed between the end part of the isolation 11 and the channel stop region 13a. In this way, by providing the offset region 20 of low impurity density, the dispersion of depletion region and the durability to high voltage at the P-N junction part are ensured.
Another proposal is disclosed in, for example, Japanese Patent Application Laying Open Gazette No.2-15672 as shown in FIGS. 15(a)-(d). FIG. 15(a) is a plan view of the semiconductor device, FIG. 15(b),(c) and (d) are respectively sections taken along lines XVb--XVb, XVc--XVc and XVd--XVd. Each figure shows that a part 22 adjacent to the drain region 16 of an overlap region 21 where the isolation 11 and the gate electrode 12 overlap each other is a part of the offset region 20 to which an impurity is lightly doped. Wherein, a part 23 adjacent to the source region 15 of the overlap region 21 is not a part of the offset region 20 but a part of the channel stop region 13a to which an impurity is comparatively-lightly doped.
The above semiconductor devices, however, have following problems.
Referring to the construction according to the former reference, in FIG. 14(c), at the overlap region 21 between the isolation 11 and the gate electrode 12, the low-density impurity (e.g. boron of p-type impurity in n-channel FET) in the offset region 20 is diffused into the isolation 11 to lower the density of a face-boundary of the offset region 20 when thermal oxidation of silicon is conducted to form the isolation 11. When an inversion layer is generated because of further lowering of the impurity density of the offset region 20, a leakage current may occur between the drain region 16 and the source region 15 via the overlap region 21. Also, in the process, a side wall spacer must be provided at each side wall of the silicon nitride layer 31 for forming LOCOS in order to form the offset region 20 (refer to FIG. 2(c) in the reference), which needs two additional steps for forming and removing the side wall spacer.
Referring to the latter reference, in the overlap region 21 where the end part of the isolation 11 and gate electrode 12 overlap each other, the channel stop region 13a is extended to a part 23 excepting a part 22 adjacent to the drain region 16, so that the inversion layer at the part 23 is prevented and the leakage current between drain and source is also prevented.
In this case, however, as well as in the case of the former reference, since the channel stop region 13a is formed in such a shape, a photoresist mask having a special shape must be formed, which needs an additional step. Further, in order to define the part 22 adjacent to the drain region 16 and the part 23 adjacent to the source region 15 in the overlap region 21 where the end part of the isolation 11 and the gate electrode 12 overlap each other, a mask for patterning the silicon nitride layer and a mask for forming the gate electrode must be aligned accurately. However, the gate electrode is getting narrower and narrower in width accompanied by micro-fabrication of transistor, which results in difficult alignment.